Method for packaging hermetically sealed integrated circuit chip

Metal working – Method of mechanical manufacture – Electrical device making

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Details

174 52PE, 174 52FP, H05K 328

Patent

active

040795110

ABSTRACT:
An assembly line method for fabricating hermetically sealed integrated circuit chips with externally extending terminal leads comprising the steps of securing at least one integrated circuit chip upon a spider assembly; stamping a strip of iterative lead frame assemblies from a strip of flat stock metal; encapsulating each of said lead frame assemblies with plastic in a configuration which leaves a window space in the center thereof or defined elsewhere therein, with the convergent ends of the individual conductive paths of the lead frame extending out of the plastic and into said window space, and the divergent ends of such conductive paths extending out of the plastic and away from the window space; mounting the terminal chip holding spider assembly onto the convergent ends of the conductive paths of the lead frame; inserting a first cap over the window space on one side of the encapsulating plastic; filling the window space with a sealant to completely immerse said spider bearing chip therein and having the properties of being electrically insulative and virtually completely resistant to the passage of moisture therethrough; and inserting a second cap over said window space on the other side of said encapsulating plastic to completely seal said spider bearing chip therebetween in said sealant.

REFERENCES:
patent: 3509430 (1970-04-01), Mroz
patent: 3627901 (1971-12-01), Happ
patent: 3763404 (1973-10-01), Aird
patent: 3767839 (1973-10-01), Beal
patent: 3778685 (1973-12-01), Kennedy
patent: 3802069 (1974-04-01), Thompson
patent: 3832480 (1974-08-01), Bunker

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