Method for fabrication of CMOS devices having minimized drain co

Details Method for fabrication of CMOS devices having minimized drain co Method for fabrication of CMOS devices having minimized drain co

1995-01-19

1996-11-12

Fourson, George

Fishing, trapping, and vermin destroying

437 34, 437 56, 437 58, 437 67, 437187, 437203, 148DIG50, 257338, 257351, 257357, 257369, H01L 2170

Patent

active

055739695

ABSTRACT:
There are disclosed a semiconductor device and a method for fabrication thereof. The semiconductor device comprises an insulating film for well isolation which electrically insulates N-well from P-well, the drain electrode of PMOS and the drain electrode of NMOS being adjacent to the trench for well isolation, and a conductive wire filling one contact hole which interconnects the drain electrodes of N-well with those of P-well. The semiconductor device is very reduced in size, and thus, high integration thereof can be achieved.

REFERENCES:
patent: 4729964 (1988-03-01), Natsuaki et al.
patent: 4766090 (1988-08-01), Coquin et al.
patent: 4927777 (1990-05-01), Hsu et al.
patent: 4945070 (1990-07-01), Hsu
patent: 4980306 (1990-12-01), Shimbo
patent: 5015594 (1991-05-01), Chu et al.
patent: 5137837 (1992-08-01), Chang et al.
patent: 5384280 (1995-01-01), Aoki et al.

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