Method of forming self-aligned twin tub CMOS devices

Details Method of forming self-aligned twin tub CMOS devices Method of forming self-aligned twin tub CMOS devices

1995-05-03

1996-11-12

Trinh, Michael

Fishing, trapping, and vermin destroying

437 57, 437931, 148DIG106, H01L 218238

Patent

active

055739636

ABSTRACT:
The present invention provides a method of manufacturing twin wells in a silicon substrate which uses only one photo step and provides a smooth surface topology. The first embodiment begins by forming spaced field oxide regions in the substrate. The spaced field oxide regions define a first region and a second region. A masking layer composed of borophosphosilicate glass (BPSG) and a barrier layer are formed over the field oxide regions. The barrier layer and the masking layer over the first region are removed by a photo etch process. Then, N-type impurities are implanted into the first region forming a n-well using the barrier layer and masking layers as a mask. Then, p-type impurities are implanted into the substrate to form a p-type layer beneath the N-well and a P-well in the second region. The barrier layer and the masking layer are then removed. The substrate is then annealed to drive in the ion implanted impurities thereby forming a n-well and a p-well. A first embodiment uses a barrier layer formed of silicon nitride and a second embodiment uses a barrier layer formed of amorphous silicon.

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