Low cycle time CMOS process

Details Low cycle time CMOS process Low cycle time CMOS process

1995-12-15

1996-11-12

Trinh, Michael

Fishing, trapping, and vermin destroying

437 29, 437 57, 437164, 437931, H01L 218238

Patent

active

055739628

ABSTRACT:
A process for fabricating CMOS devices has been developed, in which decreased cycle time has been achieved, via a reduction in photomasking steps. The low cycle time CMOS process features the use of only one photo mask to create both the lightly doped, as well as the heavily doped N type, source and drain regions, by performing both implantations, after creation of the insulator sidewall spacer. In addition the P type source and drain regions are formed, using an oxide layer as a blockout for the P well region, thus eliminating the use of another photomasking procedure.

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