Low stress semiconductor device lead connection

Details Low stress semiconductor device lead connection Low stress semiconductor device lead connection

1978-07-17

1981-04-21

James, Andrew J.

357 65, 357 67, 357 68, H01L 2348, H01L 2946, H01L 2954

Patent

active

042636060

ABSTRACT:
An external connection structure for an integrated semiconductor device is disclosed. The semiconductor device includes a substrate on which a wiring layer, which is covered by an insulator layer is disposed. According to the invention, an aperture is provided in the insulative layer to expose the wiring layer. A metallic film lines the aperture, covering the exposed portion of the wiring layer and defining a recess. A bump type electrode of a malleable metal is disposed in the recess. The bump electrode is spaced from the side walls of the recess, and projects beyond the surface of the metallic film surrounding the recess for connection under pressure with an external lead plate.

REFERENCES:
patent: 3303071 (1967-02-01), Kocsis
patent: 3617818 (1971-11-01), Fuller
patent: 3629669 (1971-12-01), Kauppila
patent: 3921200 (1975-11-01), Pille
patent: 3942187 (1976-03-01), Gelsing et al.
patent: 3953877 (1976-04-01), Sigusch
patent: 4005455 (1977-01-01), Watrous et al.
patent: 4045594 (1977-08-01), Maddocks
patent: 4051508 (1977-09-01), Sato et al.
patent: 4060828 (1977-11-01), Satonaka
IBM Technical Disclosure Bulletin; by Ainslie, vol. 11, No. 10, Mar. 1969, p. 1339.

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