Multilayer circuit structure having projecting via lead

Details Multilayer circuit structure having projecting via lead Multilayer circuit structure having projecting via lead

1995-06-07

1996-10-08

Ryan, Patrick

Stock material or miscellaneous articles

Structurally defined web or sheet

Discontinuous or differential coating, impregnation or bond

428901, 428210, 361748, B32B 900

Patent

active

055629709

ABSTRACT:
A multilayer structure is fabricated by forming a conductive layer on an insulative substrate. A first conductive pattern is formed on the first conductive layer and a resist layer having a via hole therethrough is formed on the first pattern. A via lead is formed in the via hole by electrically plating a metal therein utilizing the first layer as a lead for the plating process. The resist and the exposed part of the first layer are removed and a polyimide layer having a thermal expansion coefficient that is equal to that of the via lead is formed over the substrate. The surface of the polyimide layer is etched until the via lead top segment protrudes to a predetermined height above the surface of the etched polyimide layer. A second pattern is formed on the polyimide layer and the exposed lead segment by a plating process.

REFERENCES:
patent: 4879156 (1989-11-01), Herron et al.
patent: 4908940 (1990-03-01), Amano et al.
patent: 4933228 (1990-06-01), Katagiri
patent: 5117069 (1992-05-01), Higgins, III
Websters II, New Riverside Dictionary, p. 1156.
6th IEEE/CHMT International Electronic Manufacturing Technology Symposium, 26 Apr. 1989, NARA, JP pp. 128-131; N. Iwasaki et al.: "A pillar-shaped via structure in a cu-polymide multilayer substrate".
IBM Technical Disclosure Bulletin, vol. 20, No. 9, Feb. 1978, New York US, pp. 3443-3444; M. M. Haddad: "Selectively electroplating pad terminals on an MLC substrate.".
IBM Technical Disclosure Bulletin, vol. 32, No. 6B, Nov. 1989, New York US, pp. 326-327; "Additive plating on chromium for circuitizing non-epoxy substrates.".

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