Multiplier decoding using parallel MQ register

Details Multiplier decoding using parallel MQ register Multiplier decoding using parallel MQ register

1979-12-31

1982-06-08

Smith, Jerry

Boots, shoes, and leggings

364760, G06F 752

Patent

active

043342841

ABSTRACT:
There is described a floating point processor architecture which permits multiple bit shifting over strings of binary 1's and strings of binary O's in a single machine cycle. During a multiply operation, an MQ register (arranged in parallel) which stored the multiplier, shifts the multiplier out for decoding at a rate comparable to the rate at which the partial product is shifted. This is made possible by using a parallel MQ register so that two bits may be shifted per clock cycle. This architecture permits extremely fast multiplication by using a multiple bit shift architecture while minimizing hardware requirements.

REFERENCES:
patent: 3192363 (1965-06-01), MacSorley
patent: 3725649 (1973-04-01), Deerfield
patent: 3730425 (1973-05-01), Kindell et al.
patent: 4075704 (1978-02-01), O'Leary
patent: 4208722 (1980-06-01), Rasala et al.

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