Number theoretic processor

Boots – shoes – and leggings

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235311, 340347DD, H03K 1324

Patent

active

042813913

ABSTRACT:
Input data is converted into its modular equivalents. These equivalents are used to perform the desired computation in a modular manner. Each computation is done for several moduli. The various modular results are woven into a mixed radix version of the answer. This version of the answer is then converted into a normal radix equivalent.
The processor is constructed from a network of nodes. These nodes either store constants, perform modular arithmetic, or perform three operand binary arithmetic. The nodes are organized in networks to perform encoding, modular computations, residue to mixed radix decoding, and mixed to normal radix conversion. These operations are performed in a parallel manner. The function of the nodes can be performed by table lookup. The table lookups can be implemented with memories. The interconnection of the nodes is structured to facilitate the construction and modification of such processors. Processors can be implemented to perform many types of operations. Processors which perform summation, inner products, determinate evaluation, and summation of the squares of differences are discussed.

REFERENCES:
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patent: 3700872 (1972-10-01), May
patent: 3750111 (1973-07-01), Kobylar et al.
patent: 3758766 (1973-09-01), Combet
patent: 3882483 (1975-05-01), Burke et al.
patent: 3943350 (1976-03-01), Lanning
patent: 3980874 (1976-09-01), Vora
patent: 4107783 (1978-08-01), Huang
Banerji, Sign Detection in Residue Number Systems, IEEE Transactions on Computers, vol. C-18, No. 4, Apr. 1969, pp. 313-320.
Jullien, Residue Number Scaling and Other Operations Using ROM Arrays, IEEE Transactions on Computers, vol. C-27, No. 4, Apr. 1978, pp. 325-336.

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