High speed serial data synchronization scheme

Details High speed serial data synchronization scheme High speed serial data synchronization scheme

1975-06-25

1977-03-29

Miller, Charles D.

Communications: electrical

Audible indication

Percussion-type sound producer

G06F 504

Patent

active

040152529

ABSTRACT:
A serial-to-parallel data conversion and synchronization scheme in which a lurality of active logic elements are utilized as delay lines. Each of the delay lines introduces a delay equal to the period of one data bit and one additional delay line introduces a delay equal to one half the period of a data bit. The input of the first delay line is connected to the data input of a first flip-flop and the outputs of each of the plurality of delay lines are each connected to the data input of a flip-flop. The output of the additional delay line is connected to the clock inputs of each of the flip-flops whereby the serial data word is converted to a parallel data word and the conversion is internally clocked by the delay lines themselves.

REFERENCES:
patent: 2635229 (1953-04-01), Gloess
patent: 2827233 (1958-03-01), Johnson
patent: 3160876 (1964-12-01), Stochel
patent: 3182306 (1965-05-01), Bartlett
patent: 3226709 (1965-12-01), Brightman
patent: 3261913 (1966-07-01), Reichert
patent: 3492422 (1970-01-01), Mason
patent: 3792362 (1974-02-01), Grant

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