Digital phase comparing apparatus

Details Digital phase comparing apparatus Digital phase comparing apparatus

1979-07-05

1981-07-28

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307528, 307579, 307246, 307247R, 331 1A, 328133, H03K 526, H03L 718

Patent

active

042812593

ABSTRACT:
A digital phase comparator, to be used in a phase locked loop, for example, comprises a first and second input signal terminals receiving a first and second input signals, respectively, the phases of which are to be compared, and a pair of first and second delay flip-flops. The first input signal terminal is connected to a clock terminal of the first delay flip-flop and a reset or set terminal of the second delay flip-flop. The second input terminal is connected to a set or reset terminal of the first delay flip-flop and a clock terminal of the second delay flip-flop. An inverted or non-inverted output terminal of the first delay flip-flop is connected to a data terminal of the second delay flip-flop. An inverted or non-inverted output terminal of the second delay flip-flop is connected to a data terminal of the first delay flip-flop. An output signal associated with the phase difference between the first and second input signals is obtained from the output terminals of the first and second delay flip-flops.

REFERENCES:
patent: 3610954 (1971-10-01), Treadway
patent: 3641443 (1972-02-01), Zerby
patent: 3714463 (1973-01-01), Laune
patent: 4122405 (1978-10-01), Tietz

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