Digital circuit for performing multicycle addressing in a digita

Details Digital circuit for performing multicycle addressing in a digita Digital circuit for performing multicycle addressing in a digita

1994-12-08

1996-11-19

Robertson, David L.

39542101, G06F 934

Patent

active

055772285

ABSTRACT:
The architecture of the cache memory of the present invention includes a data RAM, a TAG RAM, a controller and pad logic on a single integrated circuit chip. The cache memory is coupled to a CPU and a memory bus controller over a host bus. The host bus receives read data from the cache memory and provides write data to the cache memory. The cache memory controller provides signals to the memory bus controller to indicate whether data accessed by the CPU resides in the cache memory. The present invention increases memory speed by allowing circuit elements in the cache memory to operate during both phases of a system clock signal.

REFERENCES:
patent: 4977498 (1990-12-01), Rastegar et al.
patent: 5091851 (1992-02-01), Shelton et al.
patent: 5170476 (1992-12-01), Laakso et al.
patent: 5392414 (1995-02-01), Yung
patent: 5450555 (1995-09-01), Brown, III et al.
patent: 5471591 (1995-11-01), Edmondson et al.
Intel Corporation, IntelDX4.TM. Processor Data Book, Feb 1994, pp. 6-1 to 6-5.

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