Patent
1995-10-31
1996-11-19
Beausoliel, Jr., Robert W.
395250, 395376, 395670, G06F 1100, G06F 930, G06F 900, H01J 100
Patent
active
055772005
ABSTRACT:
A number of data misalignment detection circuits are provided to select ones of an execution unit and memory order interface components, of an out-of-order (OOO) execution computer system, this aids the buffering and fault generation circuits of the memory order interface components, to buffer and dispatch load and store operations depending on if the misalignments are detected and their nature, resulting in load and store operations of misaligned data against a memory subsystem of the OOO execution computer system are available, the data addressed by the load and store operations are of the following types: chunk split, cache split, or page split misaligned.
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Abramson Jeffrey M.
Akkary Haitham
Glew Andrew F.
Hinton Glenn J.
Konigsfeld Kris G.
Beausoliel, Jr. Robert W.
Intel Corporation
Wright Norman M.
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