Multiple data registers and addressing technique therefore for b

Details Multiple data registers and addressing technique therefore for b Multiple data registers and addressing technique therefore for b

1994-09-28

1996-11-19

Tung, Kee M.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395507, 345201, G06F 1206

Patent

active

055771939

ABSTRACT:
A frame buffer construction and data storage technique for computer graphics display systems are presented employing a plurality of on-chip color registers. The plurality of on-chip color registers facilitate block writing and flash writing of multiple color information into the main frame buffer video memory. Addressing of the plurality of color registers is achieved at a column address strobe (CAS) cycle page mode rate for both the loading of the registers and the block or flash writing of the contents of the registers into the main memory array.

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