System and method for selecting and buffering even and odd instr

Details System and method for selecting and buffering even and odd instr System and method for selecting and buffering even and odd instr

1994-08-26

1997-04-01

Kim, Ken S.

395800, 395391, G06F 938

Patent

active

056175493

ABSTRACT:
The present invention is directed to a system and method for selecting instruction words from a memory system for simultaneous execution in an execution unit of a computer system. In one example, an instructor selector unit of the present invention employs an addressing unit to fetch instructions from an instruction cache. The instructor selector unit also employs a receiver unit for buffering and transferring multiple aligned as well as misaligned instructions. The instruction selector unit supplies these instructions to an instruction execution unit (having an integer unit and a floating point unit), which is capable of executing two bundled instructions simultaneously. The instruction selector unit can provide instructions to the instruction execution unit individually, or as a bundled pair.

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Superscalar Microprocessor Design, Mike Johnson, Chapter 3, Developing an Execution Model, pp. 31-55, 1991 by Prentice Hall, Inc.
A High Speed Superscalar PA-RISC Processor, Eric DeLano, Will Walker, Jeff Yetter, Mark Forsyth, pp. 116-121, IEEE Computer Society, 10662 Los Vaqueros Circle, P.O. Box 3014, Los Alamitos, CA 90720-1264.

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