Patent
1995-06-02
1997-04-01
Davis, George B.
395 24, G06F 1518
Patent
active
056175124
ABSTRACT:
A neural array processor computing structure with a plurality of processing units which have orthogonal sets of neurons and communicating adder trees which provide a reverse communication path. Each processing unit has a weight storage unit. The processing units are arranged so that they are connected to the weight storage units in symmetric pairs. General processing cells share communication paths so that a reduced number of communicating adder trees is used.
REFERENCES:
patent: 4858147 (1989-08-01), Conwell
patent: 5170463 (1992-12-01), Fujimoto et al.
Duranton et al, "A General Purpose Digital Architecture for Neural Network Simulations", 1st IEE Inter. Conf-on Artificial Neural Networks, 16-18 Oct. 1989.
Pechanek Gerald G.
Vassiliadis Stamatis
Augsburger Lynn
Davis George B.
International Business Machines - Corporation
Phillips Steven B.
Shkurko Eugene I.
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