System for combining independently clocked simulators

Details System for combining independently clocked simulators System for combining independently clocked simulators

1989-09-22

1992-01-14

Lall, Parshotam S.

Boots, shoes, and leggings

G06F 1516

Patent

active

050816012

ABSTRACT:
Two or more independently clocked simulators are interconnected in a manner which prevents signal exchange at a time when the internal simulation clocks of the simulators point to different times on a simulated time line. Each simulator transmits to one or more of the other simulators in its network information indicaitng the next point in simulated time at which the transmitting simulator can model a state change which might affect a model part being simulated by the receiving simulator. Blocking means are provided for blocking the receiving simulator from advancing its simulated time clock ahead of the next state change time of the transmitting simulator. The receiving simulator is free, however, to operate at its maximum speed for simulated time spans occurring before the next state change time of the transmitting simulator.

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Arnout et al; "The Use of Threshold Functions and Boolean-Controlled Network Elements for Macromodeling of LSI Circuits"; IEEE 1978.
Menzel et al; "A Multilevel Simulation for MOS VLSI Networks"; IEEE 1989.
Chadha et al.; "M.sup.3 -A Multi-Level Mixed-Mode Simulator"; IEE Conference on Computer-Aided Design 1988.
Sampson; "An Ideal Mixed-Mode Simulator" VLSI System Design 1988.

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