Standard cell LSI layout method

Details Standard cell LSI layout method Standard cell LSI layout method

1990-06-06

1991-09-10

Lall, Parshotam S.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

050479490

ABSTRACT:
In a standard cell LSI including functional circuits formed by placing a group of cell rows consisting of standard cells selected from a group of standard cells and by routing the standard cells, a standard cell LSI layout method including the steps of comparing the routing density in routing areas located between the cell rows and bending the cell rows by shifting one or more of the standard cells in a direction of a more dispersed routing area from a more congested routing area. The cell rows are bent at a point between each high congested area of the routing area which encloses the cell rows depending on the routing density. A link cell may be provided for linking power and ground pins of the standard cells which have been shifted in position and which compose the bent cell rows. The link cell may be stored in a library in a system of composing the cell rows by storing the standard cells in a library and referring to the standard cells from the library in defining a standard cell LSI layout.

REFERENCES:
patent: 4613941 (1986-09-01), Smith et al.
patent: 4636965 (1987-01-01), Smith et al.
patent: 4686629 (1987-08-01), Noto et al.
"A Routing Program Applicable to Various Chip Structures of Gate Arrays" by Terai et al., Joho Shori Gakkai, Ronbunshi, vol. 25, No. 3, May 1984, pp. 357-364.
"An Over-Cell Gate Array Channel Router" by Krohn et al., IEEE 20th Design Automation Conference, 1983, pp. 665-670.
"Rectilinear Area Routing: A Channel Router Approach" by Hudson et al., IEEE, 1985, pp. 468-471.
"A Dense Gate Matrix Layout Method for MOS VLSI" by Lopez et al., IEEE Trans. Electron Devices, vol. ED-27, pp. 1671-1675, Aug. 1980.

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