Use of a polysilicon layer for local interconnect in a CMOS or B

Details Use of a polysilicon layer for local interconnect in a CMOS or B Use of a polysilicon layer for local interconnect in a CMOS or B

1990-07-26

1992-01-14

James, Andrew J.

357 68, H01L 2904, H01L 2348

Patent

active

050815180

ABSTRACT:
A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BICMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconencts. A conformal silicon dioxide layer is subsequently deposited and etched for forming oxide spacers on the sidewalls of the polysilicon layer. By selectively doping the polysilicon layer and exposed portions of the substrate, a continuous active region is formed beneath the polysilicon layer and the sidewall spacers.

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El-Diwany et al., "Use of the Polysilicon Gate Layer for Local Interconnect in CMOS Technology Incorporating LDD Structures" IEEE Transaction, Sep. 1988, pp. 1556-1558.

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