Method for preparing complementary semiconductor device

Details Method for preparing complementary semiconductor device Method for preparing complementary semiconductor device

1979-10-17

1981-07-28

Dean, R.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148 15, 148187, 148190, 357 42, 357 59, 357 91, H01L 2122, H01L 21265

Patent

active

042802725

ABSTRACT:
A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

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patent: 3919008 (1975-11-01), Iwamatsu
patent: 4064525 (1977-12-01), Kano et al.
patent: 4097314 (1978-06-01), Schlesier et al.
Lin et al., "Shielded Silicon Gate Complementary Mos . . . Circuit", IEEE Trans. Electron Dev., vol. ED-19, No. 11, Nov. 1972, pp. 1199-1207.

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