High strength low stress encapsulation of interconnected semicon

Details High strength low stress encapsulation of interconnected semicon High strength low stress encapsulation of interconnected semicon

1990-08-27

1991-09-10

James, Andrew J.

357 69, H01L 2328, H01L 2348

Patent

active

050478346

ABSTRACT:
A semiconductor packaging technique employing a high Young's modulus, localized, external connection to pad, bond immobilizing member, together with, as needed, a low Young's modulus environmental protection covering member. A chip of Si or GaAs has an annulus of high Young's modulus epoxy over the line of external connections such as beam leads or wire bonds near the edge and a coating of silicone over the entire chip surface including the annulus.

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The Microelectronics Packaging Handbook, edited by R. R. Tummala and E. J. Rymaszewski, published by Van Nostrand (1989) pp. 409-431 "Tape Automated Bonding".
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