Semiconductor memory device having a trench-stacked capacitor

Details Semiconductor memory device having a trench-stacked capacitor Semiconductor memory device having a trench-stacked capacitor

1989-08-14

1991-09-10

James, Andrew J.

357 51, 357 55, H01L 2968

Patent

active

050478150

ABSTRACT:
A semiconductor memory device includes a capacitor and an insulating separation area in a trench formed around a switching transistor, with a storage electrode of the capacitor being sandwiched between an upper and a lower cell plate electrode to reduce leakage current due to the parasitic MOS transistor effect in the trench sidewall along the channel in the switching transistor and leakage current due to the gate-controlled diode effect in the trench sidewall. Also, a method is disclosed for manufacturing such semiconductor memory device.

REFERENCES:
patent: 4873560 (1989-10-01), Sunami et al.
patent: 4918502 (1990-04-01), Kaga et al.
Kaga et al., "Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring", Aug 1988, IEEE Transactions on Electron Devices, pp. 1257-1263.
Shigeru Nakajima, "An Isolation-Merged Verticle Capacitor Cell for Large Capacity DRAM" IEDM Technical Digest 1984 pp. 240-243.

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