Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

1989-12-28

1991-09-10

Prenty, Mark

357 90, H01L 2910

Patent

active

050478133

ABSTRACT:
A base layer is formed as first and second base layers through two steps, so that only an upper base layer (second base layer) can be easily set in high impurity concentration dissimilarly to conventional one. As the result, a JFET effect can be suppressed. Further, first and second well regions are formed for the first and second base layer, respectively, to be coupled with each other to form a single well region, so that a lower well region (first well region) can be easily set higher in impurity concentration than an upper well region (second well region). As the result, a latch-up phenomenon can be prevented.

REFERENCES:
patent: 4587713 (1986-05-01), Goodman et al.
patent: 4684413 (1987-08-01), Goodman et al.
"Insulated Gate Transistor Modeling and Optimization", IEDM Digest, Dec. 1984, 10.5, pp. 274-277, by Yilmay et al.
"Improved COMFETs with Fast Switching Speed and High-Current Capability", IEDM 83, 4.3, pp. 79-82, by Goodman et al., Dec. 1983.
"The Insulated Gate Transistor: A New Three-Terminal MOS-Controlled Bipolar Power Device", IEEE Transactions on Electron Devices, vol. ED-31, No. 6, Jun. 1984, pp. 821-828, by Baliga et al.

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