Mode dependent minimum FIFO fill level controls processor access

Details Mode dependent minimum FIFO fill level controls processor access Mode dependent minimum FIFO fill level controls processor access

1996-04-16

1997-04-01

Saras, Steven

Computer graphics processing and selective visual display system

Display driving control circuitry

Physically integral with display elements

345201, G09G 300

Patent

active

056171188

ABSTRACT:
A full screen of video data is stored in a video memory. A small block of video data to be imminently displayed on a raster scan display device is copied, two double-words (32 bits) at a time, from the video memory to a 6 by 32-bit first in, first out buffer (FIFO). A fill detection circuit determines when the fill level of the FIFO is at or above certain predetermined levels; specifically, 3, 5 and 6 double-words. The current operating mode is stored in a programmable mode register wherein each mode corresponds to a unique screen resolution. For example, one mode corresponds to a 1024 by 768 pixel resolution having 256 colors per pixel, while another mode corresponds to a 320 by 200 pixel resolution having 4 colors per pixel. A minimum fill level is selected by a level selection circuit depending on the current operating mode. Since the FIFO is emptied quickly in a high resolution mode, a higher minimum fill level is selected for high resolution modes than for low resolution modes. Processor access circuitry permits a central processor to write new video data to the video memory. The processor access circuitry, however, is disabled whenever the current fill level is below the minimum fill level set by the level selection circuit. Thus, central processor access to the video memory is only permitted when there is a minimum level of data in the FIFO, and that minimum level of data is selected according to the current operating mode.

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