Memory configuration for display information

Details Memory configuration for display information Memory configuration for display information

1994-09-29

1997-04-01

Nguyen, Chanh

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

345 98, G09G 336

Patent

active

056171137

ABSTRACT:
Image data or addressing signal information for a dual-scan display (110, 168) is stored in three half-frame buffers (114a, 114b, and 114c; 172a, 172b, and 172c). Each of two buffers contains complete display information, comprising either image data or column signal data, for section 126B or 126T of the display. The third buffer receives and stores image data or column signals for a subsequent frame for one of the two display sections. By offsetting the frame periods of the two independent display sections, both display sections have display information corresponding to a complete frame without requiring two complete frame buffers, thereby reducing cost, size, and complexity of the display.

REFERENCES:
patent: 4630122 (1986-12-01), Morokawa
patent: 4740786 (1988-04-01), Smith
patent: 4745485 (1988-05-01), Iwasaki
patent: 4816816 (1989-03-01), Usui
patent: 4908710 (1990-03-01), Wakai et al.
patent: 5262881 (1993-11-01), Kuwata et al.
patent: 5387923 (1995-02-01), Mattison et al.

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