Boots – shoes – and leggings
Patent
1990-11-29
1993-04-06
Fleming, Michael R.
Boots, shoes, and leggings
395725, 3642405, 3642715, 364DIG1, 36492691, 364DIG2, G06F 900
Patent
active
052010368
ABSTRACT:
A data processor (1) includes a wait state control unit (6) for generating a ready signal for instructing a bus control unit (3) to insert a wait state into a bus cycle being performed. The bus control unit performs a bus cycle with first and second states (T1 and T2). The wait state control unit includes a bus cycle judgement circuit, a register, a wait cycle selector/decoder, a wait cycle presence/absence detector for detecting whether or not a wait state is to be inserted into the bus cycle, and a ready signal generator for generating a ready signal in response to the detection signal from the wait cycle presence/absence detector for generating the ready signal in response to the detection signal irrespective of the absence of the decoded wait cycle number from the wait cycle selector/decoder. Thus, the wait cycle presence/absence detector, which detects only the requirement of the insertion of a wait state, causes the ready signal to be generated to the bus control unit even though the number of wait states has not been decoded by the end of the second state.
REFERENCES:
patent: 4787032 (1988-11-01), Culley
patent: 4802120 (1989-01-01), McCoy
patent: 5032982 (1991-07-01), Dalrymple et al.
patent: 5070473 (1991-12-01), Takano et al.
Electronic Engineering, Mar. 1983, pp. 103-105.
Auve Glenn A.
Fleming Michael R.
NEC Corporation
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