Method of forming side dielectrically isolated semiconductor dev

Details Method of forming side dielectrically isolated semiconductor dev Method of forming side dielectrically isolated semiconductor dev

1998-04-24

2000-07-11

Everhart, Caridad

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

438439, H01L 2176

Patent

active

060872411

ABSTRACT:
A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.

REFERENCES:
patent: 4630356 (1986-12-01), Christie et al.
patent: 5236862 (1993-08-01), Pfiester et al.
patent: 5358892 (1994-10-01), Rolfson
patent: 5399520 (1995-03-01), Jang
patent: 5683933 (1997-11-01), Seino
patent: 5707889 (1998-01-01), Hsu et al.
PCT International Search Report dated Aug. 31, 1999.

Affiliated with

Also associated with

Rating

Method of forming side dielectrically isolated semiconductor dev does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming side dielectrically isolated semiconductor dev, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming side dielectrically isolated semiconductor dev will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-541825