Method of making edge-connected integrated circuit structure

Details Method of making edge-connected integrated circuit structure Method of making edge-connected integrated circuit structure

1989-07-20

1992-01-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 2, 437 4, 437203, 437204, 437226, 437233, H01L 2144

Patent

active

050810634

ABSTRACT:
A focal plane array and an associated technique for manufacturing such an array, employ a first, substantially planar semiconductor substrate, that contains a densely compacted array of photodiodes, interconnected with a plurality of second semiconductor substrates in which the signal processing electronics for the array are formed. The backside of the focal plane array-containing substrate has an associated array of conductive bumps to which the respective photodiodes on the imaging side are electrically connected. Within plural ones of second semiconductor substrates, each of which is associated with a respective row of the array of photodiodes there are integrated the signal processing electronics for that row. Formed along side edge portions of the second substrates are a plurality of metallic bumps which are conductively connected to the signal processing electronics. Each signal processing substrate is conductively joined to the photodiode chip by corresponding bumps that have been electroplated along the side edge portion of that second semiconductor substrate to internal conductive regions that terminate at that side edge portion. Each conductive region is preferably comprised of doped semiconductor material which extends to the side edge portion of the substrate and is connected to regions of the signal processing devices within the semiconductor substrate.

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