Method of manufacturing an insulated gate field effect transisto

Details Method of manufacturing an insulated gate field effect transisto Method of manufacturing an insulated gate field effect transisto

1991-01-16

1992-01-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 69, 437 70, 437 72, H01L 21336

Patent

active

050810588

ABSTRACT:
An insulated gate field effect transistor surrounded by a field silicon oxide layer which is at least partially embedded in a silicon substrate, is disclosed. A pair of silicon oxide layers thinner than the field silicon oxide layer and thicker than the gate insulating film are formed on both end portions of the channel region in the channel width direction, and the gate electrode is formed on the gate insulating film and extends on the pair of silicon oxide layers and on the field silicon oxide layer.

REFERENCES:
patent: 4216573 (1980-08-01), Joshe et al.
patent: 4326329 (1982-04-01), McElroy
patent: 4551910 (1985-11-01), Patterson
patent: 4758530 (1988-07-01), Schubert

Affiliated with

Also associated with

Rating

Method of manufacturing an insulated gate field effect transisto does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing an insulated gate field effect transisto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing an insulated gate field effect transisto will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-541244