Method of making electrically-erasable, electrically-programmabl

Details Method of making electrically-erasable, electrically-programmabl Method of making electrically-erasable, electrically-programmabl

1991-01-31

1992-01-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 49, 437 63, 437 70, 437191, H01L 21265, H01L 21336

Patent

active

050810553

ABSTRACT:
An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ration of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio. Isolation between cells in the wordline direction is by a self-aligned implanted region, in this embodiment.

REFERENCES:
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4317272 (1981-03-01), Kuo et al.
patent: 4326331 (1982-04-01), Guterman
patent: 4750024 (1988-06-01), Schreck
patent: 4822750 (1989-04-01), Perlegos et al.
patent: 4849369 (1989-07-01), Jeuch et al.

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