Method for forming interconnect for integrated circuits

Details Method for forming interconnect for integrated circuits Method for forming interconnect for integrated circuits

1991-12-17

1993-04-06

Griffin, Donald A.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

437192, H01G 406, H01L 21285

Patent

active

052008800

ABSTRACT:
According to the present invention, a thin conductive layer is formed over an underlying structure in an integrated circuit. The underlying structure can be either a semiconductor substrate or an interlevel interconnect signal line. An insulating layer is deposited over the device. The insulating layer is patterned and etched in order to expose a portion of the underlying conductive layer and to define an interconnect signal line. When the signal line locations are etched away, the thin conductive layer acts as an etch stop and protects the underlying structure. A metal refill process can be used to then form interconnects and contacts within the etched interconnect lines. This results in interconnect and contacts having upper surfaces which are substantially coplanar with the upper surface of the insulating layer in which they are formed.

REFERENCES:
patent: 4920072 (1990-04-01), Keller et al.
patent: 5005067 (1991-04-01), Sakata et al.
patent: 5110762 (1992-05-01), Nakahara et al.
patent: 5112765 (1992-05-01), Cederbaum et al.

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