Method for forming emitters in a BiCMOS process

Details Method for forming emitters in a BiCMOS process Method for forming emitters in a BiCMOS process

1989-02-03

1991-09-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437162, 437950, 437933, 437 57, 148DIG151, 148DIG123, 148DIG124, H01L 21328, H01L 21225

Patent

active

050473573

ABSTRACT:
A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species. The emitter electrode according to the invention can also be exposed to the opposite conductivity type source/drain implant, with reduced sensitivity to counterdoping.

REFERENCES:
patent: 4279671 (1981-07-01), Komatsu
patent: 4369072 (1983-01-01), Bakeman, Jr. et al.
patent: 4452645 (1984-06-01), Chu et al.
patent: 4484388 (1984-11-01), Iwasaki
patent: 4818720 (1989-04-01), Iwasaki

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