Method of forming conductor lines of a semiconductor device

Details Method of forming conductor lines of a semiconductor device Method of forming conductor lines of a semiconductor device

1990-06-05

1992-01-14

Tufariello, T. M.

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating has specified thickness variation

205125, 205266, C25D 502

Patent

active

050807633

ABSTRACT:
A method of forming conductor lines of a semiconductor device comprises a step of depositing (electroplating) a gold (Au) layer on an underlying barrier conductive layer in a gold plating bath. According to the present invention, the plating bath is supplemented with an additive in amount such that a lead (iron or nickel) concentration of the bath is form 0.7 to 10 ppm, whereby a deposition rate of the gold near a patterned resist layer is lowered, in comparison with that at the center part of the uncovered conductive layer. The gold plated layer has round edges at the both corners thereof, and therefore, when a protective insulating layer is formed over the gold plated layer, the round edges improve the step coverage of and prevent the appearance of cracks in the protective layer.

REFERENCES:
patent: 4767507 (1988-08-01), Wilkinson

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