Floating-gate memory array with silicided buried bitlines

Details Floating-gate memory array with silicided buried bitlines Floating-gate memory array with silicided buried bitlines

1991-07-26

1993-04-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 48, 437195, H01L 21265, H01L 2170

Patent

active

052003507

ABSTRACT:
A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

REFERENCES:
patent: 4373248 (1983-02-01), McElroy
patent: 4426764 (1984-01-01), Kosa et al.
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4851365 (1989-07-01), Jeuch
patent: 5023680 (1991-06-01), Gill et al.
Sze "VLST Technology" McGraw-Hill Book Company, second edition, New York, 1988, p. 267 and p. 495.

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