Hardware switch level simulator for MOS circuits

Details Hardware switch level simulator for MOS circuits Hardware switch level simulator for MOS circuits

1987-05-04

1990-03-06

Gruber, Felix D.

Boots, shoes, and leggings

371 23, G06F 1516, G01R 3128

Patent

active

049071807

ABSTRACT:
A hardware switch level simulator for LSI/VLSI MOS circuits capable of simulating circuits with pass transistors and performing timing analysis. The simulator has a stack memory containing lists of nodes to be operated on, a solve unit having programmed logic arrays for performing simulation steps using Bryant algebra plus an addition step for detecting unblocked paths to a controlling gate of a pass transistor, a traversal unit having gate memory storing a gate list of nodes for each transistor and having link memory storing a netlist of transistor switches with parameters such as preset transistor switch state, transistor strength, and pointers to nodes to which a transistor connects. A timing unit performs delay calculations. In order to simulate pass transistor circuits, the traversal unit has two sets of memory addressing gates. One set ordinarily accesses link memory, while a second set ordinarily addresses gate memory. During source to gate path detection, the second set can be multiplexed to also address link memory.

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Bryant, IEEE Transactions on Computers, vol. C-33, No. 2, Feb. 1984, "A Switch Level Model and Simulator for MOS Digital Systems", pp. 160-177.
Dally et al., IEEE Transactions on Computer-aided Design, vol. CAD-4, No. 3, Jul. 1985, "A Hardware Architecture for Switch-level Simulation", pp. 239-250.
Lin et al., IEEE Transactions of Computer-aided Design, vol. CAD-3, No. 4, Oct. 1984, "Signal Delay in General RC Networks", pp. 331-349.
Smith, Proceedings of the IEEE International Conference on Computer Design, 1985, "Adaptation of a Switch Level Model for Digital Circuits Utilizing Steering Logic", pp. 586-589.
Yamamoto et al., IEEE Transactions on Computer-aided Design, vol. CAD-4, No. 3, Jul. 1985, "Vectorized LU Decomposition Algorithms for Large-scale Circuit Simulation," pp. 232-238.

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