Bit-serial integrator circuitry

Details Bit-serial integrator circuitry Bit-serial integrator circuitry

1987-08-24

1989-06-20

Laroche, Eugene R.

Boots, shoes, and leggings

377 49, 377 72, G06F 750

Patent

active

048414662

ABSTRACT:
A bit-serial integrator includes the cascade combination of a bit-serial adder, a first bit-serial register and a second bit-serial register. Input signal is applied to one input of the adder and the output terminal of the second bit-serial register is coupled to a second input of the adder. A transparent latch is coupled to an output of the first bit-serial register and is conditioned to pass a predetermined number of sample bits and then to latch and output a particular sample bit for the duration of a sample period. The output of the latch is an integrated, scaled and truncated representation of the input signal.

REFERENCES:
patent: 3757261 (1973-09-01), Sather
patent: 4023019 (1977-05-01), Leibowitz et al.
patent: 4246642 (1981-01-01), Magill
H. Urkowitz, "Analysis & Synthesis of Dela-Line Periodic Filters", IRE Transactions on Circuit Theory, Jun. 1957, pp. 41-53.
D. A. Linden & B. D. Steinberg, "Synthesis of Delay Line Networks", IRE Transactions on Aeronautical & Navigation Electronics, Mar. 1957, pp. 34-39.

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