Boots – shoes – and leggings
Patent
1987-06-16
1989-06-20
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 15332
Patent
active
048414654
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a transformation circuit arrangement for the transformation of a first unknown vector (A) with the aid of a matrix (B.sup.2).
The publication, NTZ Archiv, Volume 3 (1981), No. 1, pages 9 et seq. discloses a novel function system (m functions) and its use for image transmission. With the aid of feedback connected shaft registers, bivalent periodic pulse sequences can be generated. By orthonormalizing these sequences, one obtains an orthonormal, binary function system which serves as the basic function system for a signal transformation (m transformation), similarly to a Fourier or Walsh transformation.
SUMMARY OF THE INVENTION
It is the object of the invention to provide a transformation circuit which permits the transformation of vectors with little circuitry requirements.
This is accomplished by the above circuit arrangement wherein the matrix B.sup.2 has rows containing a second, known vector B which is cyclically shifted by rows, both vectors having the same length, and the first vector (A) is divided into partial vectors (P), with each partial vector (P) being fed to an addition circuit and to a longic linkage circuit connected to the outpur of the addition circuit. The output of the linkage circuits are fed to a calculating unit which furnishes the transform T as the result. Advantageous modifications of the invention are discussed further hereunder.
According to the invention, a known vector is transformed with an unknown vector in that a matrix is constructed in such a manner that a known vector is cyclically shifted by rows and thus a square matrix is constructed. The transformation of the unknown vector with the thus constructed matrix produces the transform in a manner realizable with simple circuitry. According to the invention, it is assumed that both vectors have the same length N and the vector constructing the matrix is present in binary form. To simplify the circuit, the unknown vector is divided into P groups each having a length R. The length of the groups is less than the total length of the vector. The last group is filled cup with zeros if necessary.
For parallel processing, the individual groups are each fed to an addition stage. The output signals are fed to a calculating unit, via logic linkage circuits, e.g. simple wiring, and possibly--if the linkage circuits all have the same configuration--with a decording circuit switched according to a modulo-R relationship connected to their outputs. The number to be divided in the modulo-R relationship is the number of elements of the water. The calculating unit furnishes the transform as its output signal.
If the individual groups are processed serially, only one addition stage and one linkage circuit are required. The individual groups of the vector are multiplexed and fed, in accordance with the modulo-R relationship, to an accumulator and to a register which furnishes the transform.
With these measures it is accomplished that circuitry requirements are reduced since the multiplication operations to be performed of necessity are not required for the transformation of vectors.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention, the invention will be described in greater detail below with reference to the drawing figures. It is shown in:
FIG. 1, a block circuit diagram for parallel processing;
FIG. 2, the structure of an addition circuit;
FIG. 3, a formation law for the addition circuit;
FIG. 4, a square matrix;
FIG. 5, a formation law for the linkage circuit;
FIG. 6, a logic linkage circuit;
FIG. 7, a calculating unit; and
FIG. 8, a block circuit diagram for serial processing.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 is a block circuit diagram for the transformation of an unknown vector A with the aid of a matrix B.sup.2. All elements a(i) of vector A are read into a buffer 1 and are there divided into groups 2, 3, and 4, each having a length R. Groups 2, 3, 4 are each fed to an addition circuit 5, 6, 7. The outputs of addition circuits
REFERENCES:
patent: 3742201 (1973-06-01), Groeinsky
patent: 4062060 (1977-12-01), Nussbaumer
patent: 4646256 (1987-02-01), Bracewell
Harkcom Gary V.
Shaw Dale M.
Telefunken Fernseh und Rundfunk GmbH
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