Boots – shoes – and leggings
Patent
1980-09-29
1983-05-10
Thomas, James D.
Boots, shoes, and leggings
G06F 1300
Patent
active
043832970
ABSTRACT:
In a multi-processor system of the type in which each processor is provided with its own unique bus which has an addressing system organized in such a manner that all store locations and peripheral equipments are addressed as part of a comprehensive single addressing system. Each address comprises a module number and an offset address. Each module in the system includes a module number comparator which detects the presence of its module address on a CPU bus and allows the offset address to be active within that module. The invention provides for the incorporation of similar mechanisms within a CPU allowing the CPU to address its own internal registers in an identical manner to its normal bus addressing mode. In addition the offset address includes a "bit portion address" which selects a mask which is used when performing the required internal register operation. The main advantage of such an arrangement is the simplification of the instruction range for the CPU as "normal" instructions may be used to manipulate the internal registers rather than having special purpose instructions dedicated to the manipulating of the registers.
REFERENCES:
patent: 3614741 (1971-10-01), McFarland, Jr.
patent: 3854126 (1974-12-01), Gray et al.
patent: 4194241 (1980-03-01), Mager
Andrews Martyn P.
Wheatley Nigel J.
Eng David Y.
Plessey Overseas Limited
Thomas James D.
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