Bit dispersement method for enhanced SEC-DED error detection and

Details Bit dispersement method for enhanced SEC-DED error detection and Bit dispersement method for enhanced SEC-DED error detection and

1989-08-30

1993-04-06

Gregory, Bernarr E.

Excavating

365200, G11C 2900

Patent

active

H00011762

ABSTRACT:
Improved error detection and correction is obtained in computers of the type possessing multi-bit memory devices. The error detection involves dispersing the bits from each multi-bit memory device in such a way that a SEC-DED codeword can detect when the multi-bit memory device fails.

REFERENCES:
patent: 3812336 (1974-05-01), Bossen et al.
patent: 4006467 (1977-02-01), Bowman
patent: 4485471 (1984-11-01), Singh et al.
patent: 4488298 (1984-12-01), Bond et al.
patent: 4489403 (1984-12-01), Bond
patent: 4506364 (1985-03-01), Aichelmann, Jr. et al.
patent: 4584682 (1986-04-01), Shah et al.
patent: 4802170 (1989-01-01), Trottier
patent: 4835627 (1989-05-01), Endo et al.
Singh et al., Word Line, Bit Line Address Interchanging to Enhance Memory Fault Tolerance, IBM Tech. Discl. Bulletin, vol. 26, No. 6, Nov. 1983, pp. 2747-2748.
Franco, Coding for Error-Free Communications, Electro-Technology, Jan. 1968, FIG. 7.

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