System for logic synthesis-for-testability capable of improving

Details System for logic synthesis-for-testability capable of improving System for logic synthesis-for-testability capable of improving

1997-11-10

2000-02-22

Teska, Kevin J.

39550003, 39550019, G06F 1750

Patent

active

060289880

ABSTRACT:
In a logic synthesis-for-testability system including a memory unit (101) for memorizing, as an objective circuit description which is logically synthesized, an FSM (finite state machine) description having a plurality of states, a testability improving unit (106) includes a candidate selecting unit (111) for selecting candidate states among the plurality of states with an asynchronous reset state of the plurality of states excluded from the candidate states. The testability improving unit improves a testability of the FSM description by reducing an average distance between all pairs of the plurality of states by selecting (112) a center state from the candidate states and providing (113) the FSM description with new transitions, each of which is directed to the center state from each of the plurality of states other than the center state. The candidate selecting unit may select the candidate states among the plurality of states with the asynchronous reset state and near states of the plurality of states excluded from the candidate states. Each of the near states has a distance which is calculated from the asynchronous reset state to each of the near states and which is shorter than a predetermined threshold value.

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