Electrostatic discharge (ESD) protection for a 5.0 volt compatib

Details Electrostatic discharge (ESD) protection for a 5.0 volt compatib Electrostatic discharge (ESD) protection for a 5.0 volt compatib

1998-07-13

2000-02-22

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, H02H 322

Patent

active

060287586

ABSTRACT:
An electrostatic discharge (ESD) protection circuit is provided for a 5.0 volt compatible I/O buffer with transistors made using a 2.5 volt process. The ESD circuit includes a lateral NPN bipolar junction transistor (BJT) 750 which provides a path to ground during ESD without experiencing gate oxide damage, since BJTs do not have a gate oxide as do CMOS transistors. The lateral NPN BJT is formed in a p- epitaxial layer of a p type substrate. The lateral NPN BJT functions to turn on during ESD due to charge up of the p- epitaxial region. The ESD protection circuitry further includes circuitry 722, 724, and 725-727 to clamp the pad voltage to a maximum value during an ESD event to prevent damage to the gate oxide of the 2.5 volt process CMOS transistors. The ESD protection circuit further includes stacked NMOS transistors 700A-H and 702A-H coupled by ballast resistors 701A-H and 703A-H between a power supply pin voltage and the pad. The ballast resistors prevent a single pair of pull up transistors from entering secondary breakdown before other pairs turn on. The ESD protection circuit can further include a p+ guard ring 901-903 surrounding each pair of NMOS pull up transistors. The p+ guard ring prevents one pair of transistors from entering breakdown similar to the ballast resistors.

REFERENCES:
patent: 4939616 (1990-07-01), Rountree
patent: 5452171 (1995-09-01), Metz et al.
patent: 5629545 (1997-05-01), Leach

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