Integrated circuit and layout system therefor

Details Integrated circuit and layout system therefor Integrated circuit and layout system therefor

1992-04-20

1994-07-19

Black, Thomas G.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

053315723

ABSTRACT:
In the chip layout of an LSI, a layout near bonding pads is efficiently optimized. Especially in a chip having a large number of pins, an increase in chip size caused by pad necks can be prevented. Normal functional macro-blocks are arranged in an inner region of the LSI. On the other hand, input/output blocks including corner blocks are arranged at the peripheral portion of the LSI. In addition, pads separated from the input/output blocks are arranged on the LSI including portions near the corner blocks, and the input/output blocks and the pads are connected to each other through wiring lines.

REFERENCES:
patent: 3629843 (1971-12-01), Scheinman
patent: 3644937 (1972-02-01), Isett
patent: 4910680 (1990-03-01), Hiwatashi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 4942317 (1990-07-01), Tanaka et al.
patent: 5124273 (1992-06-01), Minami
patent: 5164907 (1992-11-01), Yabe
Deborah C. Wang, "Pad Placement and Ring Routing for Custom Layout", 27th ACM/IEEE Design Automation Conference, pp. 193-199, 1990.

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