Boots – shoes – and leggings
Patent
1987-11-25
1990-05-29
Heckler, Thomas M.
Boots, shoes, and leggings
G06F 1324
Patent
active
049300709
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to an interrupt control method for a multiprocessor system, and more particularly, to an interrupt control method for a multiprocessor system, which enables each processor to recognize an interrupt without using a special interrupt control line.
As systems employing processors become more and more sophisticated and complex, multiprocessor systems are used wherein a plurality of processors is used in a single system. In such a multiprocessor system, the processors employed are interconnected by a bus. For effecting an external interrupt, therefore, each processor requires a special dedicated line for interrupts. The more CPUs used, the more such special interrupt lines are needed, resulting in increased hardware and lowered system flexibility.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an interrupt conrol method for a multiprocessor system, which solves the aforesaid problems, does not use any dedicated lines, and provides a higher degree of flexibility.
According to the present invention, the above problems can be solved by an interrupt control method for a multiprocessor system in which a plurality of processors and an interface circuit for causing interrupts are connected to a bus, the method including the steps of using a particular address space as an interrupt address, selecting a mask bit corresponding to the address space in each processor, storing the mask bit in a register in the processor, allowing a bus cycle generator circuit in the interface circuit to occupy the bus in response to an interrupt signal, writing a bit, indicative of a cuase of the interrupt signal and corresponding to the address space, into an address bus, and enabling the processor to recognize an interrupt signal from the address bus bit corresponding to the address space and the mask bit stored in the register.
With the above method, when an interrupt is caused, the bus cycle generator circuit in the interface circuit writes data into the address bit corresponding to the cause of the interrupt. Since the address space is defined as an interrupt address, the processor recognizes the interrupt, compares the address with the mask bit stored in the register in the processor, and recognizes the interrupt as an interrupt applied to itself. Therefore, no special hardware control line for interrupts is required.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagrm of an embodiment of the present invention; and
FIG. 2 is a detailed block diagram of an interrupt control circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENT
An embodiment of the present invention will hereinafter be described in specific detail with reference to the drawings.
FIG. 1 is a block diagram of an embodiment according to the present invention. An interface circuit 10 for receiving an external interrupt signal has control circuits 11, 12, and 13 for receiving respective interrupt signals IS1, IS2, and IS3.
A processor board 20 has therein a CPU1 21, a selector circuit (SC) 22, a decoder circuit 23, and a mask bit register 24. The decoder circuit 23 decodes an address bus input, compares it with the data stored in the mask bit register 24, and recognizes whether there is an interrupt signal applied to the processor 20.
Processor boards 30 and 40 are identical in structure to the processor board 20, and include CPU2 31 and CPU3 41, selector circuits 32 and 42, decoder circuits 33 and 43, and mask bit registers 34 and 44.
The interface circuit 10 and the processors 20, 30 and 40 are interconnected by a bus 4 comprising address buses, data buses, and commands such as READ and WRITE.
Operation will now be described below. Addresses Addr1, Addr2 and Addr3 in the entire address space are allotted to an interrupt. When an external interrupt signal IS2 is applied to the interrupt control circuit (IC2) 12, the interrupt control circuit 12 occupies the buses, and writes bit data Addr 2 corresponding to the interrupt signal IS2 into the address bus, and simultaneously wri
REFERENCES:
patent: 4268904 (1981-05-01), Suzuki et al.
patent: 4769768 (1988-09-01), Bomba et al.
Patent Abstracts of Japan, vol. 6, No. 112 (P-124) [990], Jun. 23, 1982; and JP-A-57 41 727 (Hitachi Seisakusho K.K.) 09-03-1982.
Patent Abstracts of Japan, vol. 9, No. 243 (P-392) [1966], Sep. 30, 1985; JP-A-60 95 678 (Mitsubishi Denki K.K.) 29-05-1985.
Kinoshita Jiro
Yonekura Mikio
Fanuc Ltd.
Heckler Thomas M.
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