Rugged lateral DMOS transistor structure

Details Rugged lateral DMOS transistor structure Rugged lateral DMOS transistor structure

1989-04-05

1990-05-29

Larkins, William D.

357 234, 357 20, H01L 2978

Patent

active

049299913

ABSTRACT:
A lateral DMOS transistor includes a high conductivity substrate having an epitaxial layer grown thereon to have a resistivity suitable for the transistor body. A highly doped topside body contact is diffused into the epitaxial layer along with an abutting heavily doped source. The source is self-aligned with a conductive polysilicon gate lying on top of a thin gate oxide. After source diffusion the gate is oxide coated so as to be fully insulated. A main drain electrode portion is diffused near the opposing side of the gate spaced a distance away. A lightly doped drain region portion extends between the main drain region and the edge of the gate providing the required surface breakdown behavior. The main drain diffusion portion is extended into the epitaxial layer so that the spacing between the heavily doped substrate and the drain diffusion produces depletion region reach through at a voltage that is lower than the drain avalanche voltage. Several embodiments are set forth for practicing the invention.

REFERENCES:
patent: 4686551 (1987-08-01), Mihara
patent: 4767722 (1988-08-01), Blanchard
patent: 4803532 (1989-02-01), Mihara
patent: 4819044 (1989-04-01), Murakami

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