1988-06-30
1990-05-29
Larkins, William D.
357 45, H01L 2704, G11C 1140
Patent
active
049299905
ABSTRACT:
A semiconductor memory device comprises a semiconductor substrate, four memory cells arranged in point symmetry on the main surface, each of the memory cells having one transistor (6) formed around the point of symmetry and one capacitor adjacent to the outside of the transistor (6), the capacitor having a surface capacitor region (4a) parallel to the main surface and a trench capacitor region (40a) parallel to a side wall of a trench (40) formed in the main surface along the outer periphery of the surface capacitor region (4a), and an insulating layer (10) covering the memory cells and having one contact hole (2) arranged at the center of the point symmetry, with the contact hole (2) enabling electrical contact to each transistor (6).
REFERENCES:
patent: 4651183 (1987-03-01), Lange et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4751557 (1988-06-01), Sunami et al.
patent: 4763178 (1988-08-01), Sakui et al.
IBM Technical Disclosure Bulletin, vol. 28, No. 8, Jan. 1986, pp. 3385, 3386.
Larkins William D.
Mitsubishi Denki & Kabushiki Kaisha
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