Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1998-05-11
2000-02-22
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257751, 257752, 257762, 257763, H01L 2348, H01L 2352
Patent
active
060283629
ABSTRACT:
A method of fabricating a semiconductor device includes the steps of: providing a substrate having an insulating layer thereon; forming a connection hole including a first sub-hole and a second sub-hole mutually connected in the insulating layer, wherein the first sub-hole has a first diameter and the second sub-hole has a second diameter larger than the first diameter; forming a first conductive layer over the substrate; removing the first conductive layer to a thickness so as to form a side wall spacer film on a side wall of the second sub-hole and a plug film in the first sub-hole; forming a barrier metal layer over the substrate to cover the side wall spacer and the plug film; forming a second conductive layer over the substrate to fill space in the connection hole; and chemical mechanical polishing the second conductive layer.
REFERENCES:
patent: 5173442 (1992-12-01), Carey
patent: 5262354 (1993-11-01), Cote et al.
patent: 5427981 (1995-06-01), Choi
patent: 5529953 (1996-06-01), Shoda
patent: 5534461 (1996-07-01), Kuwajima
patent: 5602053 (1997-02-01), Zheng et al.
patent: 5637924 (1997-06-01), Hibino
patent: 5686354 (1997-11-01), Avanzino et al.
patent: 5689140 (1997-11-01), Shoda
patent: 5693563 (1997-12-01), Teong
patent: 5705849 (1998-01-01), Zheng et al.
K. Ueno, et al., "A Quarter-Micron Planarized Interconnection Technology With Self-Aligned Plug", IEDM 1992, pp. 305-308.
T. Zettler, et al., "Self-Reconstructing Metallization--A Novel Planar Process for VLSI Metallization", VMIC Conference, Jun. 8-9, 1993, pp. 359-365.
A. Krishnan, et al., "Copper Metallization for VLSI Applications", VMIC Conference, Jun. 9-10, 1992, pp. 226-231.
K. Suguro, et al., "Cu Inlaid Interconnections Formed by Dual Damascene", ULSI Research Laboratories, Manufacturing Engineering Research Center, Semiconductor Division, Toshiba Corporation, pp. 42-47 date not available.
K. Kikuta, et al., "Aluminum-Germanium-Copper Multilevel Damascene Process Using Low Temperature Reflow Sputtering and Chemical Mechanical Polishing", IEDM 1994, pp. 101-104.
Thomas Tom
Vu Hung Kim
Yamaha Corporation
LandOfFree
Damascene wiring with flat surface does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Damascene wiring with flat surface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Damascene wiring with flat surface will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-522769