Differential CMOS peak detection circuit

Details Differential CMOS peak detection circuit Differential CMOS peak detection circuit

1993-03-16

1994-07-19

Callahan, Timothy P.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307359, 307494, H03K 524

Patent

active

053312104

ABSTRACT:
A fully differential CMOS peak detection circuit has a differential input stage and a negative feedback loop that form a differential unity gain feedback amplifier. The differential output of the differential input stage is applied to a differential peak detect circuit having a pair of series diode/capacitor combinations. The diode/capacitor junctions are applied to differential inputs of the negative feedback loop. A common mode correction circuit is coupled to the differential CMOS peak detection circuit to minimize differences between the common mode voltages of the differential input stage and the negative feedback loop. The differential peak voltage is held at the differential output of the differential input stage for sampling by a sampling circuit during a readback interval, and then tracks a differential input signal applied to the differential input of the differential input stage during a tracking interval. The differential peak detection circuit then peak detects during a peak detect interval that is equal to a desired sample time window.

REFERENCES:
patent: 4271488 (1981-06-01), Saxe
patent: 4598215 (1986-07-01), Schechtman et al.
patent: 4634895 (1987-01-01), Luong
patent: 4808848 (1989-02-01), Miller
patent: 5144525 (1992-09-01), Saxe et al.
Article, "Meeting 2-ns Pulse Capture Requirements" Joseph R. Peter Oct. 7, 1985 issue of Nikkei Electronics. pp. 9-12, FIGS. 5, 6, 7.

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