Hierarchical netlist extraction tool

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Details

3642831, 3642832, 364489, 364DIG1, G06F 1560

Patent

active

053013182

ABSTRACT:
The present invention is directed to a method and apparatus for providing a general netlist extraction tool which generates tool-specific incremental and hierarchical netlist extractors. The present invention comprises three main functional modules; a netlist scheduler, a netlist extractor and a netlist binder. The netlist scheduler traverses the design tree to check for updated hierarchical blocks in the design by comparing the schematic sheet dates with the netlist file dates. Only updated blocks are scheduled for incremental netlisting. The netlist extractor expands and extracts the netlist of the updated blocks only. The netlist binder binds all the netlist files into a single complete netlist file using tool-specific hierarchical netlist input syntax. The netlist binder also integrates information about monitoring nodes, stimuli, models, external subcircuits and analysis statements from a user-provided, single tool control file. The present invention provides a hierarchical netlist file which preserves schematic hierarchy, making it easy to correlate simulation results with the schematics. The incremental mode of the present invention reduces total simulation and netlisting time. By doing incremental and hierarchical netlisting, run time memory, as well as disk space requirements, are reduced.

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L. G. Chen et al. "Hierarchial Functional Veri. for Cell-Based Design Styles" IEE Proc.-G. Circuit & System, v.1341 part G, No. 1, Feb. 1987, pp. 103-109.

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