Manufacturing process for a micro MIS type FET

Details Manufacturing process for a micro MIS type FET Manufacturing process for a micro MIS type FET

1992-11-20

1994-07-19

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437913, 148DIG53, H01L 21265

Patent

active

053309235

ABSTRACT:
A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

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