Method and device for assigning I/O address in data processing a

Details Method and device for assigning I/O address in data processing a Method and device for assigning I/O address in data processing a

1991-06-17

1994-04-05

Shaw, Dale M.

G06F 1502

Patent

active

053012763

ABSTRACT:
An I/O address assigning device in a data processing apparatus having a standard port provided in the main unit for connecting the main unit to an I/O address assigning device so as to increase the function of the data processing apparatus and an I/O connecting portion for connecting an additional board provided with an I/O port therein. The I/O address assigning device comprises a control means for disabling the I/O port in the main unit for operation in order to prevent conflict of the I/O port in the main unit and on an additional board which have the same address, a detecting means for detecting the preset I/O address of the additional I/O port in the state in which the I/O port in the main unit is disabled, and an address assigning means for assigning an I/O address different from the preset address of the additional I/O port which is detected by the detecting means to the I/O port in the main unit. When the I/O address of the standard port on the additional board which is detected by the detecting means in the state in which the standard port in the main unit is disabled is the same as the I/O address of the standard port in the main unit, an I/O address different from that of the standard port on the additional board is assigned to the standard port on the main unit.

REFERENCES:
patent: 4556953 (1985-12-01), Caprio et al.
patent: 4760553 (1988-07-01), Buckley et al.
patent: 4775931 (1988-10-01), Dickie et al.
patent: 4964038 (1990-10-01), Louis et al.
patent: 5038320 (1991-08-01), Heath et al.
"Parity Check Circuit for Detecting Missing Feature Cards", L. C. Eggerbrecht et al., p. 4366, line 1-15. IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980, pp. 4366-4368.

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