Circuit for multiframe synchronization

Details Circuit for multiframe synchronization Circuit for multiframe synchronization

1992-03-27

1994-04-05

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

375116, H04J 306

Patent

active

053011953

ABSTRACT:
A synchronization circuit for a multiframe signal based upon a multiframe synchronization pattern of a plurality of frame bits inserted in the multiframe signal at a predetermined period is disclosed. A shift register(11) stores and sequentially shifts state data each representing degree of the synchronization, the number of states corresponding to the number of the frame bits. The value of the multiframe synchronization pattern expected for the input at the each state up to establishment of the multiframe synchronization is stored in a memory(14). The past state data for the predetermined period is read out from the shift register in response to an input of the multiframe signal. In a state decision circuit(13), the value of the multiframe synchronization pattern for the read out state data is read out from the memory. The value of the read out multiframe synchronization pattern and the input multiframe signal is compared, the state data representing the subsequent transition state is applied to the input of the shift register in response to the coincident detection, and determines establishment of multiframe synchronization when the state transition to a predetermined state occurs.

REFERENCES:
patent: 4744081 (1988-05-01), Buckland
patent: 4794626 (1988-12-01), Tanabe et al.
patent: 4984238 (1991-01-01), Watanabe et al.
patent: 5020057 (1991-05-01), Taniguchi et al.
patent: 5113395 (1992-05-01), Murakami et al.
patent: 5128945 (1992-07-01), Enns et al.

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